The present invention relates to a system for decoding a moving picture signal which is coded by using a variable length code for an image communication, transmission and storage, and more particularly to a system for decoding a moving picture signal which is generated by multiplexing a discrete cosine transform (DCT) coefficient and additional data, such as an H.261 system and a moving picture expert group (MPEG) system.
FIG. 1 is a block diagram showing an example of coding a moving picture signal in accordance with the H.261 and MPEG systems, in which the H.261 and MPEG are a standardization committee for coding a moving picture signal.
There will be described below a coding system shown in FIG. 1. An original picture signal S.sub.1, which is input through an input terminal 1 at every macro-block, is divided into one which is input into a motion compensation determination circuit 3 as it is, and the other which is input into a motion compensation circuit 2. The motion compensation circuit 2 performs a motion prediction on the basic of a content of a reference image memory 4 so as to output a motion compensation residual signal S.sub.2, a motion vector signal S.sub.3 and a reference image signal S.sub.4. The motion compensation determination circuit 3 receives the original signal S.sub.1 and the residual signal S.sub.2 after the motion compensation and determines as to whether or not a motion compensation should be performed, so as to output a selected signal S.sub.5 and a flag signal S.sub.6 which shows a selection of any of the signals. A discrete cosine transform (DCT) circuit 5 divides the selected signal S.sub.6 into small blocks and performs a DCT transformation so as to output a DCT coefficient signal S.sub.7. A quantization circuit 6 quantizes the DCT coefficient signal S.sub.7 to generate and output a quantized value signal S.sub.8 to a scanning conversion circuit 10 and an inverse quantization circuit 7. The scanning conversion circuit 10 scans the quantized value signal S.sub.8 with zigzags to output a scanning result to a variable length coding circuit 11. The variable length coding circuit 11 encodes and multiplies the scanning result scanned with zigzags, the flag signal S.sub.6 showing the determination flag for the motion compensation and the motion vector signal S.sub.3 so as to output a coded output S.sub.10.
On the other hand, the inverse quantization circuit 7 inversely quantizes the quantized value signal S.sub.8 so as to output an inversely quantized result to an inverse DCT circuit 8. The inverse DCT circuit 8 performs an inverse DCT transformation so as to output an inverse DCT result to a local decode signal generation circuit 9. The local decode signal generation circuit 9 receives the reference image signal S.sub.4, the flag signal S.sub.6 and the inverse DCT result, and adds the reference image signal S.sub.4 with the inverse DCT result so as to output a local decode signal S.sub.8 when the motion compensation is performed. When the motion compensation is not performed, the local decode signal generation circuit 9 makes the local decode signal S.sub.9 from the inverse DCT result as it is. An output of the local decode signal generation circuit 9 is stored in the reference image memory 4.
FIG. 2 shows a conventional system for decoding the moving picture signal which is encoded by the method shown in FIG. 1 and corresponding to the coding as the standardization of the moving picture.
A coded image signal is input through an input terminal 21 to a variable length code decoding circuit 22 which decodes a variable length code, so as to divide the coded image signal into a DCT coefficient signal S.sub.11 and an additional data signal S.sub.12. The DCT coefficient signal S.sub.11 is inverted its scanning in a scanning conversion circuit 23, is inversely quantized in an inverse quantization circuit 24, and is inversely transformed a discrete cosine transform, thereby outputting a result to a decoded signal generation circuit 26. The additional data signal S.sub.12 is supplied to an additional data redundancy decompression circuit 27 which decompresses the data signal S.sub.12 to generate a motion compensation determination flag signal S.sub.13 and a motion vector data signal S.sub.14. The motion compensation determination flag signal S.sub.13 is supplied to a motion compensation circuit 28 and the decoded signal generation circuit 26, while the motion vector data signal S.sub.14 is supplied to the motion compensation circuit 28. The motion compensation circuit 28 reads out a reference image from the reference image memory 29 on the basis of the motion vector data signal S.sub.14 to output a reference image signal S.sub.15 to the decoded signal compensation circuit 26. The decoded signal compensation circuit 26 receives the result of the inverse DCT, the reference image signal S.sub.15 and the motion compensation determination flag signal S.sub.13, and generates a decoded signal S.sub.16 by adding the reference image signal S.sub.15 with the result of the inverse DCT when the motion compensation is performed. On the contrary, when the motion compensation is not performed, the result of the inverse DCT becomes the decoded signal S.sub.16. The decoded signal S.sub.16 is also stored in the reference image memory 29 and used as a reference image when the next image is decoded.
There are the H..621 system and MPEG system as a moving picture coding system by combining the DCT and the motion compensation. All of these systems perform a coding by multiplexing the additional data and the DCT coefficient in accordance with a specific rule (syntax), respectively. When a decoding is performed, the decoding should be advanced with a sequentially analysis for a syntax of a bit stream. Furthermore, since the additional data are transmitted by taking a previous value prediction (DPCM--differential pulse code modulation--) code with a previous macro-block, it is necessary to decode the DPCM code.
Since the conventional system for decoding a signal standardized by the H.261 system has a low symbol rate after decoding a code, the variable length code decoding circuit 22 shown in FIG. 2 interprets a syntax by a serial bit to decode the variable length code, thereby realizing a compact and small scale decoding circuit.
However, even though the conventional system decodes a code with a serial bit, if the symbol rate becomes high, the variable length code decoding circuit is not in time for operation. By a simple calculation, in the variable length code decoding circuit of a serial bit type for decoding a variable length code having 10 bit of the maximum code length by a symbol rate of 27 MHz/sec after decoding, it is necessary to use a clock frequency of "27 (MHz).times.10=270 (MHz)", thereby resulting in a difficult utilization.
Accordingly, when the symbol rate is high, it is necessary to provide a variable length code decoding circuit which can decode one symbol by one clock. Even though such a circuit can be utilized by a method disclosed in Japanese Patent Application Laid-open No. 3-286855 (1991), the prior art has the problem that a circuit scale becomes larger. Accordingly, there is an attempt to suppress an increase of the circuit scale by combining a decoding circuit having a low operation speed and a small circuit scale with a decoding circuit having a high operation speed and a large circuit scale.
As described above, in the conventional moving picture decoding system, since the circuit scale becomes large if the symbol rate is high, there is provided a countermeasure to suppress the increase of the circuit scale through trial and error at a present. Especially, a moving picture reproduction system is provided as a system using the MPEG method on a display terminal of a compact disc (CD) do-it-oneself vocals audio visual system (a CD KARAOKE system) and a personal computer (PC), they are desired to be a compact size. Accordingly, the moving picture decoding circuit is made by one chip device and it is necessary to miniaturize the entire system.
On the other hand, if the syntax of bit stream is analyzed by a hardware sequencer, it becomes a special purpose chip. An MPEG syntax allows to include data which can be defined by a user. Accordingly, a syntax analyzer is desired to be able to be programmed and to use a logic calculation element such as an ALU. However, since the utilized efficiency is wrong by using the ALU only in the syntax interpretation, it is necessary to increase the utilized efficiency.